The present invention relates to a packaging structure. More specifically, the present invention relates to a packaging structure with direct electrical connections between respective active surfaces of first and second chips and between at least one of the first and second chips and a common chip.
As complementary-metal-oxide-semiconductor (CMOS) device scaling has been reduced, chip stacking methods have been explored as options for increasing system performance. In some cases, chip stacks include multiple chips arranged side-by-side to form a block with a common chip disposed at a side of the block. The block is then connected along a side of the block opposite from the common chip to a wiring board.
In chip stacks that include the common chip and multiple chips arranged in the side-by-side configuration, a large amount of silicon can be packaged and interconnected. However, the interconnections through the common (i.e., top) chip are limited by corner crossing densities. Moreover, power delivery to the common chip can be challenging since the direction of the power delivery is oriented vertically along the vertical lengths of each of the multiple chips.